Electrical and Computer Engineering
California Polytechnic State University
1 Grand Ave.
San Luis Obispo, CA 93407
I am an assistant professor in the Electrical Engineering Department at California Polytechnic State University. I recieved my PhD and MS in Electrical and Computer Engineering at the University of Illinois in Urbana-Champaign, where I worked with Rakesh Kumar in the PASSAT research group.
Fault Tolerant Systems, Scientific and High Performance Computing, Computer Architecture, Embedded Systems, Low-power Design and Architectures.
My current research focuses on algorithmic techniques and architectures for tolerating and harnessing noise in stochastic systems, especially in the context of low energy processors.
I am looking for ambitious and motivated graduate/undergraduate students. If you are a Cal Poly graduate/undergraduate student looking for an advisor or if you are someone interested in applying to Cal Poly for studies, email firstname.lastname@example.org if you want to do research in computer architecture, scientific and high performance computing, low power design, fault tolerance and/or CAD/architecture interactions. Please attach your CV as well.
- IEEE ICECS Best Paper Award (2016)
- Yi-Min Wang and Pi-Yu Chung Endowed Research Award (2013)
- Co-Chair, International Workshop on Algorithmic and Application Error Resilience (AER) June 2013
- 2012 ECE/Intel Computer Engineering Fellowship
- 2011 SRC Techcon Best Paper in Session Award (2011)
- List of Teachers Ranked as Excellent by their Students, Outstanding Ratings in Top 10%. (08-09)
- Nominated for Harold L. Olesen Award for Excellence in Undergraduate Teaching (2009)
- Tau Beta Pi (Engineering Honor Society) (2006)
- Upsilon Pi Epsilon Scholarship (Computer Science honor society) (2005)
- Iowa State President's Leadership Class (2003)
- The National Society of Collegiate Scholars (2003)
- On Undergraduate Dean's List every semester (2002-2007)
- Michael Tuttle, Braden Wicker, Majid Poshtan, Joseph Callenes "Algorithmic Approaches to Characterizing Power Flow Cyber-Attack Vulnerabilities", In the 10th IEEE Conference on Innovative Smart Grid Technolgoies, ISGT, Washington, DC. February 2019.
- Zhiqi Zhu, Joseph Callenes-Sloan and Benjamin Carrion Schafer, "Control Flow Checking Optimization Based On Regular Patterns Analysis", In the 23rd IEEE Pacific Rim International Symposium of Dependable Computing, PRDC, Taipei, December 2018.
- Sonia Mannan and Joseph Callenes-Sloan, "Treety: A Data-driven Approach to Urban Canopy Development", In the 2018 IEEE International Smart Cities Conferences, ISC2, Kansas City, September 2018.
- Farah Taher, Joseph Callenes-Sloan, and Benjamin Schaefer "A Machine Learning Based Hard Fault Recuperation Model for Approximate Hardware Accelerators", In the 54th Design Automation Conference, DAC, Austin, June 2018.
- Jiacong He and Joseph Callenes-Sloan, "Optimizing Energy in a DRAM based Hybrid Cache", In The International Symposium on Quality Electronic Design (ISQED), Santa Clara, March 2018.
- Jiacong He and Joseph Callenes-Sloan, "A Novel Architecture of Large Hybrid Cache with Reduced Energy", In the IEEE Transactions on Circuits and Systems (TCAS), July 2017. (PDF).
- Jiacong He and Joseph Callenes-Sloan, "TCache: an Energy-Efficient DRAM Cache Design", In the IEEE International Symposium on Circuits and Systems (ISCAS)", Baltimore, May 2017. (PDF).
- Jiacong He and Joseph Callenes-Sloan, "Reducing the Energy of a Large Hybrid Cache", In the IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Monte Carlo, Monaco, December 2016. (PDF). (Best Paper Award)
- Zhiqi Zhu and Joseph Callenes-Sloan. "Low Overhead Control Flow Checking Based on Regular Structured Control", In the Design, Automation, and Test in Europe Conference (DATE), Interactive Presentation. March 2016. (PDF).
- Mustafa Shihab, Jie Zhang, Shuwen Gao, Joseph Callenes-Sloan, Myoungsoo Jung, "Couture: Tailoring STT-MRAM for Persistent Main Memory", In the USENIX Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW), November 2016. (PDF).
- Farah Naz Taher and Joseph Callenes-Sloan. "Hardware Fault Compensation Using Discriminative Learning", In the 21th IEEE Pacific Rim International Symposium of Dependable Computing PRDC, Zhangiajie, November 2015. (PDF).
- Farah Naz Taher and Joseph Callenes-Sloan. "Hardware Fault Compensation Using Supervised Learning", In the 11th Workshop on Silicon Errors in Logic and System Effects (SELSE), March 2015.
- Joseph Callenes-Sloan and Hugh McNamara. "Algorithm Selection for Error Resilience in Scientific Computing", In the 20th IEEE Pacific Rim International Symposium of Dependable Computing PRDC, Singapore, November 2014. (PDF).
- Joseph Sloan, Greg Bronevetsky, and Rakesh Kumar, "An Algorithmic Approach to Error Localization and Partial Recomputation for Low-Overhead Fault Tolerance on Parallel Systems", In the 43rd Annual IEEE/FIP International Conference on Dependable Systems and Networks, DCCS-DSN, Budapest, June 2013. (PDF).
- Rakesh Kumar and Joseph Sloan. "Fortifying (even) discrete Applications against soft errors", In the SIAM Conference on Computational Science and Engineering. February 2013. (PDF). (invited)
- Ankur Sharma, Joseph Sloan, Lucas Francisco Wanner, Salma Elmalaki, Mani B. Srivastava, and Puneet Gupta, "Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware". In the 31st IEEE International Conference on Computer Design (ICCD) 2013.
- Joseph Sloan. " Algorithmic Approaches to Building Robust Applications for HPC Systems of the Future " Super Computing Dissertation Research Showcase, SC, Salt Lake City, November 2012. (PDF).
- Joseph Sloan, Rakesh Kumar,and Greg Bronevetsky. " Algorithmic Approaches to Low Overhead Fault Detection for Sparse Linear Algebra. " In the 42nd IEEE/IFIP International Conference on Dependable Systems and Networks, DCCS-DSN, Boston, June 2012. (PDF).
- Joseph Sloan, John Sartori, and Rakesh Kumar. " Exploiting Application-Level Error Tolerance in Software Design for Stochastic Processors. " In the 49th Design and Automation Conference. DAC, San Francisco, June 2012. (PDF). (invited)
- John Sartori, Joseph Sloan, and Rakesh Kumar. Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications. In the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems. CASES, Tapie, October 2011. (PDF).
- Joseph Sloan, Rakesh Kumar, Greg Bronevetsky, and Tzanio Kolev. Algorithmic Techniques for Fault Detection for Sparse Linear Algebra. In the SRC TECHCON Conference 2011. TECHCON, Austin, September 2011. (Best Paper in Session Award).
- Joseph Sloan, David Kesler, Rakesh Kumar, Ali Rahimi, A Numerical Optimization-based Methodology for Application Robustification: Transforming Applications for Error Tolerance. In the IEEE/IFIP International Conference on Dependable Systems and Networks,DCCS-DSN, Chicago, June 2010. (PDF).
- Joseph Sloan, David Kesler, Rakesh Kumar, Ali Rahimi, A Numerical Optimization-based Methodology for Application Robustification. IEEE Workshop on Silicon Errors in Logic - System Effects, SELSE, March 2010
- Joseph Sloan and Rakesh Kumar. Towards Scalable Reliability Frameworks for Error Prone CMPs. In the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES, Grenoble, October 2009. (PDF).
- John Sartori, Joseph Sloan and Rakesh Kumar. Fluid NMR - Performing Power/Reliability Tradeoffs for Applications with Error Tolerance. In the USENIX Workshop on Power-aware Computing and Systems (HotPower 2009), October 2009. (PDF).
- Joseph Sloan and Rakesh Kumar. Hardware/System Support for Four Economic Models for Manycore Computing UIUC CRHC Technical Report CRHC-07-07, December 2007.
- Served as Instructor for CPE 233 Computer Design and Assembly Language Programming (CalPoly), Winter 2018.
- Served as Instructor for CPE 133 Introduction to Digital Systems (CalPoly), Fall 2017.
- Served as Instructor for CE/EE 4370 Embedded Microprocessor Systems (UTD), Fall 2013, Fall 2014, Fall 2015, and Spring 2016.
- Served as Instructor for CE/CS/EE 6304 Computer Architecture (UTD), Spring 2014 , Spring 2015, Spring 2016, and Fall 2016.
- Served as Instructor and designed a new course, CE/EE 7304 (UTD) on Advanced Computer Architecture topics in the Spring 2015.
- Served as Course Instructor (Summer 2009) and Head TA (2008-2009) for ECE 290: Computer Engineering I (UIUC). I was included on the List of Teachers Ranked as Excellent by their Students', with Outstanding Ratings in the Top 10%. (2008-2009).
- Founder and advisor for Wide-Impact Developmental Engineering (WIDE) at UIUC. (2010-2012). Mentored several undergraduate and graduate students on ECE-related projects supporting humanitarian projects partnered with the Arial Home Foundation and other external non-profit organizations.
- Served as member of the Freshman Council Education Committee at Iowa State University of Science and Technology. (2002).
I enjoy hiking, running, climbing, and going to the theater with my wife when not working on research.